Sampling hold circuits that capture (sample) and hold analog signals have been used in analog-digital converters and the like since the past. Such a sampling hold circuit includes, for example, a transistor that outputs, from a drain thereof, an analog signal that has been input to a gate thereof and a condenser that holds the output analog signal. When a gate voltage of the transistor is fixed, fluctuation of a source voltage (i.e., the level of the analog signal) causes a gate-source voltage to fluctuate and thus an ON resistance of the transistor changes. Due to the change of the ON resistance, the level of the analog signal output from the drain is no longer proportional to the level of the analog signal input to the source, which causes accuracy of AD conversion to deteriorate. For this reason, it is desirable to maintain a constant gate-source voltage.
Therefore, a sampling hold circuit in which a bootstrap circuit is connected to a gate and a source of a transistor has been proposed (e.g., refer to Patent Literature 1). This bootstrap circuit charges a condenser by switching connection destinations of both ends of the condenser to a power supply terminal and a ground terminal when a sampling clock is at a low level. On the other hand, when the sampling clock is at a high level, the bootstrap circuit switches the connection destinations of both ends of the condenser to the source and the gate of the transistor and applies a charging voltage of the condenser between the gate and the source.